What do I do if FMF does not have the model I need?
The preferred action is to contact the manufacturer and ask them to commission FMF to create the model you need. FMF can contact the vendor but you, the customer carry more weight with them. There is a "Request a Model" link on the left side of this page you can use to send us your requirements. We will use the information you supply to encourage the vendor to sponsor the model you need. If they are unwilling to do that, you may commission the model yourself. In some cases we will already have a model that is close to what you need that you could modify.
Why do I get the following error when compiling models with ModelSim?
Constant "unitdelay01z" is type vitaldelaytype01z; expecting type vitaldelaytype01z
The ModelSim installation defaults to VITAL95. FMF models use VITAL2000. To correct the problem, edit your system or local modelsim.ini file to replace "ieee = $MODEL_TECH/../ieee" with "ieee = $MODEL_TECH/../vital2000". You may need to recompile the FMF libraries.
Where do I find the FMF libraries?
The FMF libraries can be found here.
Do I HAVE to backannotate to use these models?
No but, to ensure correct results, you must pass the correct values to the models's generics. This can be done by editing the model's instantiations in your netlist. SDF backannotation may be easier.
What is the format for writing my own ".mem" memory files?
The exact format varies from one memory to another based on memory organization,
primarily word width and address width.
However, the basics are constant and consistant with the Verilog readmem function:
Lines begining with "/" are comments;
Lines begining with "@" jump to a new address to load the next word;
Words are loaded into sequential locations unless a new address is provided.
The exact format for each model is documented in the "File Read Section" near the end of the model. Some flash memory models use more than one memory preload file.
If you are not preloading memories, it may still be neccessary to create an empty file named "none" to avoid simulation runtime errors.
What are the .ftm files and how do I make use of them?
FMF are technology independent. By this we mean they include no timing information that would bind them to a particular technology or speed grade. Instead, timing information resides in a separate file with the same name but an extention of ".ftm" or, ".ftmv" for Verilog models.
Thease timing files contain chunks of SDF (Standard Delay Format) code embedded in XML. They are designed to be both hand editable and machine readable.
The intended method of using the ftm files is through the use of the mk_sdf script which can be found, with instructions, in the FMF Tools area. mk_sdf will read a VHDL netlist and create an SDF file that can be read by a standard simulator to backannotate timing values into the simulation. However, the ftm files may also be used as a data source by those who prefer to use "cut and paste" to create their SDF files.
When I try to run some memory models, I get: "Failed to open VHDL file "none" in rb mode." What do I now?
This model allows reading a memory preload file. See item 5 for more details. The default name of the file is "none" meaning you are not preloading memory. Although this name tells the model to not read a file, the simulator still checks to see if the file exists.
To eliminate the error message, create and empty file with the name "none".
I would like to write some component models on my own. How do I learn how?
Assuming you already have a basic grasp of VHDL or Verilog, you can look at the approximately 1,000 examples found on the FMF website. If you want detailed discussion on why we model parts the way we do, try my book ASIC and FPGA Verification: A Guide to Component Modeling publish by Morgan Kaufman and available on Amazon.com.
If you do write any FMF style models, please consider sending them to us so others may benefit.
How do I use FMF models for synthesis?
The short answer is: "You don't".
FMF models are written at the behavioral level not the synthesizable Register Transfer Level (RTL) that synthesis engine support. This is done in order to achieve usable performance in board-level verification and, to avoid issues over intellectual property.
Contact Richard Munden: firstname.lastname@example.org